1. Field of the Invention
The present invention is directed to a circuit or a method according to the definition of the species in the independent claims.
The present invention relates to the detection of errors or interferences in digital circuits.
2. Description of the Related Art
Safety-critical applications require circuits which allow a detection of a present permanent or transient error. It is known from Parag K. Lala, “Self-Checking and fault tolerant digital design”, Academic Press 2001, that an invertedly doubled circuit is used for this purpose. The outputs of this circuit are identical in the case of error so that an error is signaled for a subsequent circuit. Furthermore, so-called intrinsically safe two-rail checkers are known which use two outputs to signal an error so that a fault is also detected at one of the two intrinsic outputs. In its base form, a conventional two-rail checker has two input signal pairs, each including a signal and its inverted signal, and an output signal pair for error detection. A signal pair is usually referred to as a two-rail signal. A two-rail signal is considered to be valid when its individual signals are not identical in the Boolean sense. Multiple such two-rail checkers may be combined in one circuit to check more than two input signal pairs for errors.
In FIG. 2, an equivalent circuit diagram of a conventional two-rail checker 20 having a first input two-rail signal a is shown, including an input signal a1 and an input signal a0, and a second input two-rail signal b, including an input signal b1 and an input signal b0, and an output two-rail signal y, including an output signal y1 and an output signal y0.
FIG. 1 shows a truth table 10 for a conventional two-rail checker 20. Truth table 10 shows valid output signals y0, y1 for every valid input combination of input signals a0, a1, b0, b1. The combinations illustrated in the truth table represent the error-free case, i.e., valid input signal pairs a, b may be inferred from output signal pair y. An invalid input signal pair leads to an invalid output signal pair which is detected due to its individual output signals y0 and y1 being identical. This means that if output signals show y0=1 and y1=0 or y0=0 and y1=1, an error is not present; if output signals show y0=0 and y1=0 or y0=1 and y1=1, an error is present.
FIG. 3 represents an implementation of a two-rail checker 20. Two-rail checker 20 includes four AND gates 30, 31, 32, 33 and two OR gates 34 and 35. Based on output signals y0, y1 of a two-rail checker implemented in this way, it may be detected whether input signals a0, a1, b0, b1 are valid as well as whether two-rail checker 20 works in an error-free manner. To ascertain the freedom from defects of two-rail checker 20, a test is to be carried out using the four valid input combinations.
FIG. 4 shows an error checking circuit 40 having four input signal pairs a, b, c, d. For this purpose, three two-rail checkers 20, 20′, 20″ are interconnected in a cascade and thus combined to form an output signal pair y.
FIG. 5 shows an example of a circuit 50 which includes multiple signal processing blocks 51, 52, 53, 54. An input signal Sin is processed in the circuit to yield an output signal Sout. Each signal processing block 51, 52, 53, 54 is connected to an error detection circuit 55, 56, 57, 58. Each of error detection circuits 55, 56, 57, 58 has an output signal pair d, c, b, a. Output signal pairs d, c, b, a are, in turn, input signal pairs for error checking circuit 40 and are combined to form a single output signal pair y. Output signal pair y shows whether or not an error is present in circuit 50.